This invention relates to a system for data processing, and more particularly to a separate multiport memory architecture for each of a plurality of task centers in a bus oriented, distributed data processing network.
A distributed data processing network is a preferred architecture for use of the new microprocessor technology. In a complex system, such as a spacecraft command and data system, separate microprocessors may be assigned the various tasks which are best carried out independently, but which require some communication and coordination between the task centers.
By distributing the data processing capability of a system to task centers, many instruments and sensors are converted into "intelligent" instruments and sensors. These task centers can process their own raw data to a desired extent, thus reducing the volume of raw data to be transferred for transmission, storage or further processing. In spacecraft, this reduces the load on the telemetry and communication systems. However, this limited computational ability of autonomous task centers must have communication and be coordinated with other task centers. This is best accomplished through a common bus to which each is coupled by a network bus adapter (NBA). The usual practice is to provide a buffer memory in the NBA, from which the microprocessor transfers the data to its dedicated memory for processing. Function devices associated with the microprocessor have access to that memory only under control of the microprocessor. It would be desirable to have direct memory access for each device associated with a microprocessor, as well as the microprocessor itself, on a time sharing basis.